1. Field of the Invention
The present invention relates generally to provide isolation between semiconductor components on an integrated circuit and, more particularly, to provide an isolation structure for a semiconductor integrated circuit device having high integrated density and a method of manufacturing therefor.
2. Description of the Prior Art
FIG. 1A is a partial plan view showing a designed isolation region 500 and a designed active region Ri on a silicon substrate. FIGS. 1B and 1C are partial sectional views showing a device isolation technique by a selective oxidation method, taken along the line IB--IB in FIG. 1A, (this technique being usually referred to as a LOCOS isolation method) which is described in "Isolation Technology for Scaled MOS VLSI" by W. G. Oldham, International Electron Devices Meeting, 1982, Technical Digest, pp. 216.
First, referring to the figures, in the LOCOS isolation method, a lower silicon oxide film 11 is formed by applying thermal oxidation to a silicon substrate 1. A silicon nitride film 10 having resistance to oxidation is deposited on the lower silicon oxide film 11 using a chemical vapor deposition and the like. The surface of the lower silicon oxide film 11 in a designed isolation region 500 is exposed by removing a portion of the silicon nitride film 10, using well-known photolithographic and etching processes. Boron (B.sup.+) is implanted and a channel stopper region 4 with high impurity concentration is formed in a portion of the silicon substrate 1 serving as the isolation region.
Referring to FIG. 1B, a thick field oxide film 501 is formed by applying selective thermal oxidation to the silicon substrate 1 which is masked by the silicon nitride film 10.
Referring to FIG. 1C, the silicon nitride film 10 and the lower silicon oxide film 11 are removed. A gate electrode 8 is formed through a gate oxide film on a portion serving as, for example, the channel region of the MOS transistor. N type impurity diffused regions 3a and 3b serving as the source region and the drain region, respectively, of the MOS transistor are formed. As a result, a region for isolation between devices is formed by forming the channel stopper region 4 of the same conductive type (p type in the figure) as that of the silicon substrate 1 under the field oxide film 501.
The LOCOS isolation method has been used extensively since 1970's as the device isolation technology for semiconductor integrated circuit devices. However, the following difficulties have been raised as devices have become fine and a dimension thereof has been decreased to approximately 1 .mu.m.
(a) As shown in FIG. 1B, the field oxide film 501 makes encroachment under the silicon nitride film 10 (called bird's beaks) and a finished isolation width Wia is enlarged on both sides by Wb as compared with a designed isolation width Wid and, as a result, a portion of an active region that can be formed is reduced and it becomes difficult to form a fine device. Referring to FIG. 1A, the active region is reduced from a designed active region Ri to an actual active region Ra.
(b) As shown in FIG. 1C, because of a thermal treatment for the growth of the thick field oxide film 501, a p type impurity diffused region of the channel stopper region 4 is enlarged and a junction capacitance thereof with n type impurity diffused regions 3a and 3b is increased. In addition, in a MOS (Metal Oxide Semiconductor) transistor, a narrow channel effect in which a threshold voltage rises according to decrease of a channel width becomes noticeable.
(c) As shown in FIG. 1C, because the thick field oxide film 501 having a difference in level is formed in a region for isolation between devices, the surface of the isolation region becomes non-planar. This is inconvenient for formation of a fine pattern such as a wiring.
(d) Stress occurs between the thick field oxide film 501 and the silicon substrate 1 because of a thermal treatment for the growth of the thick field oxide film 501. This often brings about a crystalline defect such as stacking fault and the like in the silicon substrate 1.
In order to solve the above described difficulties, in place of the conventional LOCOS isolation method, a trench isolation technique is proposed which is described in "Deep Trench Isolated CMOS Devices" by R. D. Rung et al., International Electron Devices Meeting, 1982, Technical Digest, pp. 237. FIG. 2A is a partial plan view showing a designed isolation region 500 and an active region R on a silicon substrate. FIG. 2B is a partial sectional view showing a trench isolation structure, taken along the line IIB--IIB in FIG. 2A.
First, referring to the figures, in the trench isolation method, a trench is formed in a portion of the silicon substrate 1 serving as the isolation region by applying anisotropic etching such as reactive ion etching, using a pattern of a thick oxide film formed on the silicon substrate 1 as a mask. Boron (B.sup.+) is implanted in the trench, using the pattern of the thick oxide film as a mask and a channel stopper region 4 with high impurity concentration is formed in a portion of the silicon substrate 1 serving as the trench. A thin silicon oxide film is formed by applying thermal oxidation to the whole surface of the silicon substrate 1. An insulating material 502 such as silicon oxide is deposited over the whole surface such that the insulating material may fully fill in the trench, using the chemical vapor deposition method and the like. Then, a photoresist is provided over the whole surface. Dry etching is made with the condition enabling an etching rate of the photoresist and that of the insulating material 502 to be equal, until the surface of the insulating material 502 is on the same level with the surface of the silicon substrate 1. As a result, the insulating material 502 is embedded inside the trench and a region for isolation between devices is formed with trench structure. Then, after a gate electrode 8 is formed through a gate oxide film on a portion serving as, for example, the channel region of the MOS transistor, n type impurity diffused regions 3a and 3b serving as the source region and the drain region, respectively, of the MOS transistor are formed.
However, in the trench isolation, it is difficult to introduce an impurity to a vertical side wall of the trench by an ion implantation method widely used in general. As a result, a leakage current is liable to flow along the side wall of the trench. In addition, because of the concentration of an electric field around the corner portion of the trench, an effect of a parasitic MOS transistor is easily generated and therefore, the leakage current is also liable to flow. In case that the concentration of an electric field occurs in the corner portions of the edge of the channel region, a threshold voltage is also liable to be decreased. Furthermore, stress occurs due to a difference between a coefficient of thermal expansion of the insulating material 502 filled in the trench and that of the silicon substrate 1. This often brings about a crystalline defect in the silicon substrate 1. Still another disadvantage is that the process of forming the trench isolation comprises complex steps as described above.
Because of the above described disadvantages, the trench isolation method needs many technological improvements and at the present, it is not widely used in manufacturing semiconductor integrated circuit devices.